HP OpenVMS MACRO Compiler Porting and User's Guide

HP OpenVMS MACRO Compiler
Porting and User's Guide

Contents

Index

C.2 Alpha PALcode Built-Ins

Alpha PALcode built-ins, primarily for privileged code, are used in the same way that Alpha instruction built-ins are used with two exceptions:

For the queue PAL functions, the compiler does not move the input arguments to the Alpha registers before issuing the PAL call as it does for all other functions. Therefore, you must supply the code to do that.
When using a built-in for a PAL call that returns a value, the source code must explicitly read R0 for the return value.

Certain Alpha PALcode built-ins, EVAX_INSQHIQR, EVAX_INSQTIQR, EVAX_REMQHIQR, and EVAX_REMQHITR, support the manipulation of quadword queues, a function that VAX MACRO does not support. If you use these built-ins, you must supply the code to move the input arguments to R16 (and R17, for EVAX_INSQxxxx), as shown in the following example:

MOVAB Q_header, R16 ; Set up address of queue header for PAL call EVAX_REMQHIQR ; Remove quadword queue entry EVAX_STQ R0, entry ; Save entry address returned in R0

The Alpha PALcode built-ins are listed in Table C-2.

Note

You can use the .DEFINE_PAL compiler directive to custom-define a built-in for an Alpha PALcode operation that is not listed in this table. See Appendix B, Specialized Directives.

On OpenVMS I64 systems, many of the built-ins are emulated with system-supplied macros.

Table C-2 Alpha PALcode Built-Ins
Built-in Operands Description

EVAX_CFLUSH <RQ> Cache flush

EVAX_DRAINA <> Drain aborts

EVAX_LDQP <AQ> Load quadword physical

EVAX_STQP <AQ,RQ> Store quadword physical

EVAX_SWPCTX <AQ> Swap privileged context

EVAX_BUGCHK <RQ> Bugcheck

EVAX_CHMS <> Change mode supervisor

EVAX_CHMU <> Change mode user

EVAX_IMB <> Instruction memory barrier

EVAX_SWASTEN <RQ> Swap AST enable

EVAX_WR_PS_SW <RQ> Write processor status software field

EVAX_MTPR_ASTEN <RQ> Move to processor register ASTEN

EVAX_MTPR_ASTSR <RQ> Move to processor register ASTSR

EVAX_MTPR_AT <RQ> Move to processor register AT

EVAX_MTPR_FEN <RQ> Move to processor register FEN

EVAX_MTPR_IPIR <RQ> Move to processor register IPIR

EVAX_MTPR_IPL <RQ> Move to processor register IPL

EVAX_MTPR_PRBR <RQ> Move to processor register PRBR

EVAX_MTPR_SCBB <RQ> Move to processor register SCBB

EVAX_MTPR_SIRR <RQ> Move to processor register SIRR

EVAX_MTPR_TBIA <> Move to processor register TBIA

EVAX_MTPR_TBIAP <> Move to processor register TBIAP

EVAX_MTPR_TBIS <AQ> Move to processor register TBIS

EVAX_MTPR_TBISD <AQ> Move to processor register, TB invalidate single DATA

EVAX_MTPR_TBISI <AQ> Move to processor register, TB invalidate single ISTREAM

EVAX_MTPR_ESP <AQ> Move to processor register ESP

EVAX_MTPR_SSP <AQ> Move to processor register SSP

EVAX_MTPR_USP <AQ> Move to processor register USP

EVAX_MFPR_ASN <> Move from processor register ASN

EVAX_MFPR_AT <> Move from processor register AT

EVAX_MFPR_FEN <> Move from processor register FEN

EVAX_MFPR_IPL <> Move from processor register IPL

EVAX_MFPR_MCES <> Move from processor register MCES

EVAX_MFPR_PCBB <> Move from processor register PCBB

EVAX_MFPR_PRBR <> Move from processor register PRBR

EVAX_MFPR_PTBR <> Move from processor register PTBR

EVAX_MFPR_SCBB <> Move from processor register SCBB

EVAX_MFPR_SISR <> Move from processor register SISR

EVAX_MFPR_TBCHK <AQ> Move from processor register TBCHK

EVAX_MFPR_ESP <> Move from processor register ESP

EVAX_MFPR_SSP <> Move from processor register SSP

EVAX_MFPR_USP <> Move from processor register USP

EVAX_MFPR_WHAMI <> Move from processor register WHAMI

EVAX_INSQHILR <> Insert entry into longword queue at head interlocked-resident

EVAX_INSQTILR <> Insert entry into longword queue at tail interlocked-resident

EVAX_INSQHIQR <> Insert entry into quadword queue at head interlocked-resident

EVAX_INSQTIQR <> Insert entry into quadword queue at tail interlocked-resident

EVAX_REMQHILR <> Remove entry from longword queue at head interlocked-resident

EVAX_REMQTILR <> Remove entry from longword queue at tail interlocked-resident

EVAX_REMQHIQR <> Remove entry from quadword queue at head interlocked-resident

EVAX_REMQTIQR <> Remove entry from quadword queue at tail interlocked-resident

EVAX_GENTRAP <> Generate trap exception

EVAX_READ_UNQ <> Read unique context

EVAX_WRITE_UNQ <RQ> Write unique context

**Table C-2 Alpha PALcode Built-Ins**
Built-in	Operands	Description
EVAX_CFLUSH	<RQ>	Cache flush
EVAX_DRAINA	<>	Drain aborts
EVAX_LDQP	<AQ>	Load quadword physical
EVAX_STQP	<AQ,RQ>	Store quadword physical
EVAX_SWPCTX	<AQ>	Swap privileged context
EVAX_BUGCHK	<RQ>	Bugcheck
EVAX_CHMS	<>	Change mode supervisor
EVAX_CHMU	<>	Change mode user
EVAX_IMB	<>	Instruction memory barrier
EVAX_SWASTEN	<RQ>	Swap AST enable
EVAX_WR_PS_SW	<RQ>	Write processor status software field

EVAX_MTPR_ASTEN	<RQ>	Move to processor register ASTEN
EVAX_MTPR_ASTSR	<RQ>	Move to processor register ASTSR
EVAX_MTPR_AT	<RQ>	Move to processor register AT
EVAX_MTPR_FEN	<RQ>	Move to processor register FEN
EVAX_MTPR_IPIR	<RQ>	Move to processor register IPIR
EVAX_MTPR_IPL	<RQ>	Move to processor register IPL
EVAX_MTPR_PRBR	<RQ>	Move to processor register PRBR
EVAX_MTPR_SCBB	<RQ>	Move to processor register SCBB
EVAX_MTPR_SIRR	<RQ>	Move to processor register SIRR
EVAX_MTPR_TBIA	<>	Move to processor register TBIA
EVAX_MTPR_TBIAP	<>	Move to processor register TBIAP
EVAX_MTPR_TBIS	<AQ>	Move to processor register TBIS
EVAX_MTPR_TBISD	<AQ>	Move to processor register, TB invalidate single DATA
EVAX_MTPR_TBISI	<AQ>	Move to processor register, TB invalidate single ISTREAM
EVAX_MTPR_ESP	<AQ>	Move to processor register ESP
EVAX_MTPR_SSP	<AQ>	Move to processor register SSP
EVAX_MTPR_USP	<AQ>	Move to processor register USP

EVAX_MFPR_ASN	<>	Move from processor register ASN
EVAX_MFPR_AT	<>	Move from processor register AT
EVAX_MFPR_FEN	<>	Move from processor register FEN
EVAX_MFPR_IPL	<>	Move from processor register IPL
EVAX_MFPR_MCES	<>	Move from processor register MCES
EVAX_MFPR_PCBB	<>	Move from processor register PCBB
EVAX_MFPR_PRBR	<>	Move from processor register PRBR
EVAX_MFPR_PTBR	<>	Move from processor register PTBR
EVAX_MFPR_SCBB	<>	Move from processor register SCBB
EVAX_MFPR_SISR	<>	Move from processor register SISR
EVAX_MFPR_TBCHK	<AQ>	Move from processor register TBCHK
EVAX_MFPR_ESP	<>	Move from processor register ESP
EVAX_MFPR_SSP	<>	Move from processor register SSP
EVAX_MFPR_USP	<>	Move from processor register USP
EVAX_MFPR_WHAMI	<>	Move from processor register WHAMI

EVAX_INSQHILR	<>	Insert entry into longword queue at head interlocked-resident
EVAX_INSQTILR	<>	Insert entry into longword queue at tail interlocked-resident
EVAX_INSQHIQR	<>	Insert entry into quadword queue at head interlocked-resident
EVAX_INSQTIQR	<>	Insert entry into quadword queue at tail interlocked-resident
EVAX_REMQHILR	<>	Remove entry from longword queue at head interlocked-resident
EVAX_REMQTILR	<>	Remove entry from longword queue at tail interlocked-resident
EVAX_REMQHIQR	<>	Remove entry from quadword queue at head interlocked-resident
EVAX_REMQTIQR	<>	Remove entry from quadword queue at tail interlocked-resident

EVAX_GENTRAP	<>	Generate trap exception

EVAX_READ_UNQ	<>	Read unique context
EVAX_WRITE_UNQ	<RQ>	Write unique context

C.3 Itanium Instruction Built-Ins for OpenVMS I64 Systems

Table C-3 Itanium Instruction Built-Ins for OpenVMS I64 Systems
Built-in Operands Description

IA64_BREAK <RQ> Generate a break instruction fault with the immediate operand provided

IA64_GETINDREG <WQ,RQ,RQ> Generate a move-from-indirect-register instruction with the first operand as the destination, the second operand as a literal ¹ specifying which indirect register file to access, and the third operand as the index into the register file

IA64_GETREG <WQ,RQ> Generate a move-from-application-register or move-from-control-register instruction with the first operand as the destination and the second operand as a literal ² specifying which application or control register to read

IA64_LFETCH
IA64_LFETCH_EXCL <RQ,RQ> Generate a line prefetch ('LFETCH') or exclusive line prefetch ('LFETCH.EXCL') instruction using the first operand as the address to prefetch and the second operand for either the reg-base-update-form or the imm-base-update-form; if the operand is the literal zero, the no-base-update-form will be used

IA64_PROBER <WQ,RQ,RQ> Generate a probe.r instruction with the first argument as the destination, the second argument as the virtual address to probe, and the third operand as the privilege level

IA64_PROBEW <WQ,RQ,RQ> Generate a probe.w instruction with the first argument as the destination, the second argument as the virtual address to probe, and the third operand as the privilege level

IA64_RSM <RQ> Generate a reset system mask ('RSM') instruction with the specified mask

IA64_RUM <RQ> Generate a reset user mask ('RUM') instruction with the specified mask

IA64_SETREG <RQ,RQ> Generate a move-to-application-register or move-to-control-register instruction with the first operand as a literal ² specifying which application or control register to write and the second operand as the value to write into the register

IA64_SRLZD <> Generate a serialize data ('SRLZD') instruction

IA64_SRLZI <> Generate a serialize instruction ('SRLZI') instruction

IA64_SSM <RQ> Generate a set system mask ('SSM') instruction with the specified mask

IA64_SUM <RQ> Generate a set user mask ('SUM') instruction with the specified mask

IA64_TAK <WK,RQ> Generate a read translation access key ('TAK') instruction

**Table C-3 Itanium Instruction Built-Ins for OpenVMS I64 Systems**
Built-in	Operands	Description
IA64_BREAK	<RQ>	Generate a break instruction fault with the immediate operand provided
IA64_GETINDREG	<WQ,RQ,RQ>	Generate a move-from-indirect-register instruction with the first operand as the destination, the second operand as a literal ¹ specifying which indirect register file to access, and the third operand as the index into the register file
IA64_GETREG	<WQ,RQ>	Generate a move-from-application-register or move-from-control-register instruction with the first operand as the destination and the second operand as a literal ² specifying which application or control register to read
IA64_LFETCH IA64_LFETCH_EXCL	<RQ,RQ>	Generate a line prefetch ('LFETCH') or exclusive line prefetch ('LFETCH.EXCL') instruction using the first operand as the address to prefetch and the second operand for either the reg-base-update-form or the imm-base-update-form; if the operand is the literal zero, the no-base-update-form will be used
IA64_PROBER	<WQ,RQ,RQ>	Generate a probe.r instruction with the first argument as the destination, the second argument as the virtual address to probe, and the third operand as the privilege level
IA64_PROBEW	<WQ,RQ,RQ>	Generate a probe.w instruction with the first argument as the destination, the second argument as the virtual address to probe, and the third operand as the privilege level
IA64_RSM	<RQ>	Generate a reset system mask ('RSM') instruction with the specified mask
IA64_RUM	<RQ>	Generate a reset user mask ('RUM') instruction with the specified mask
IA64_SETREG	<RQ,RQ>	Generate a move-to-application-register or move-to-control-register instruction with the first operand as a literal ² specifying which application or control register to write and the second operand as the value to write into the register
IA64_SRLZD	<>	Generate a serialize data ('SRLZD') instruction
IA64_SRLZI	<>	Generate a serialize instruction ('SRLZI') instruction
IA64_SSM	<RQ>	Generate a set system mask ('SSM') instruction with the specified mask
IA64_SUM	<RQ>	Generate a set user mask ('SUM') instruction with the specified mask
IA64_TAK	<WK,RQ>	Generate a read translation access key ('TAK') instruction

¹The list of valid indirect register files are located in file SYS$LIBRARY:STARLET.MLB, module $IA64REGDEF, with prefixes of IA64_REG$_INDR.
²The list of valid application and control registers are located in file SYS$LIBRARY:STARLET.MLB, module $IA64REGDEF, with prefixes of IA64_REG$_AR and IA64_REG$_CR.

Appendix D
Macros for Porting from VAX to Alpha or I64

This appendix describes macros that facilitate the porting of VAX MACRO code to an OpenVMS Alpha or OpenVMS I64 system. The macros are grouped according to their function:

Note that you can use certain arguments to the macros described in this appendix to indicate register sets. To express a register set, list the registers, separated by commas, within angle brackets. For instance:

<R1,R2,R3>

If the set contains only one register, omit the angle brackets:

D.1 Calculating Page-Size Values

The following macros provide a standard, architecture-independent means for calculating page-size dependent values:

$BYTES_TO_PAGES
$NEXT_PAGE
$PAGES_TO_BYTES
$PREVIOUS_PAGE
$ROUND_RETADR
$START_OF_PAGE

These macros reside in the directory SYS$LIBRARY:STARLET.MLB and can be used by both application code and system code. Because application code does not have access to SYSTEM_DATA_CELLS, you must supply the relevant masks, shift values, and so on.

The shift values are correlated with the page size of the processor. The rightshift values are negative; the leftshift values are positive, as shown in Table D-1.

Table D-1 Shift Values
Page size rightshift leftshift

512 bytes (VAX) -9 9

8K (OpenVMS Alpha or OpenVMS I64) -13 13

16K ¹ -14 14

32K ¹ -15 15

64K ¹ -16 16

**Table D-1 Shift Values**
Page size	rightshift	leftshift
512 bytes (VAX)	-9	9
8K (OpenVMS Alpha or OpenVMS I64)	-13	13
16K ¹	-14	14
32K ¹	-15	15
64K ¹	-16	16

¹If a future OpenVMS Alpha or OpenVMS I64 system implements this architecturally-permitted larger page size.

Typically, the application issues a call to $GETSYI (specifying the SYI$_PAGESIZE item descriptor) to obtain the CPU-specific page size and then compute other values from the page size that is returned.

The following conventions apply to the macros described in this section:

If the destination operand is blank, the source operand is used as the destination.
All macros conditionalize code on the symbols VAXPAGE and BIGPAGE.
Several macros allow for page-size-independent code on VAX systems with the independent=YES argument. These macros generate code in which I-stream fetches are changed to memory accesses. Because this is inherently slower on a VAX system, the default value of the independent argument is NO.

$BYTES_TO_PAGES

Converts a byte count to a page count.

Format

$BYTES_TO_PAGES source_bytcnt, dest_pagcnt, rightshift, roundup=YES, quad=YES

Parameters

source_bytcnt
Source byte count.
dest_pagcnt
Destination of page count.
rightshift
Location of application-provided value to shift (in place of multiply). This value is a function of the page size, as shown in Table D-1.
roundup=YES
If YES, page-size--1 is added to byte count before shifting; if NO, page count is truncated. Any other value is treated as the user-specified address of the page-size--1 value. Note that roundup=YES is incompatible with the presence of the rightshift argument; invoking the macro with both these arguments generates a compile-time warning.
quad=YES
If YES, the conversion supports 64-bit addressing. If NO, the conversion does not support 64-bit addressing.

$NEXT_PAGE

Computes the virtual address of the first byte in the next page.

Format

$NEXT_PAGE source_va, dest_va, clearbwp=NO, user_pagesize_addr, user_mask_addr, quad=YES

Parameters

source_va
Source virtual address.
dest_va
Destination of virtual address within next page.
clearbwp=NO
If YES, masks the byte-within-page portion of the source virtual address. The clearbwp=NO option is a performance enhancement, avoiding unnecessary instructions if you know you are starting on a page boundary or you are intending to divide by page-size anyway.
user_pagesize_addr
Location of the page-size value (returned by a call to the $GETSYI system service specifying the SYI$_PAGESIZE item descriptor) in the application data area. If this argument is blank, the macro uses MMG$GL_PAGESIZE (bigpage) or MMG$C_VAX_PAGE_SIZE (vaxpage).
user_mask_addr
Location of the application-provided byte-within-page mask. If this argument is blank, the macro uses MMG$GL_BWP_MASK if user_pagesize_addr is also blank. Otherwise, it subtracts 1 from the contents of the user_pagesize_addr and uses that value.
quad=YES
If YES, the conversion supports 64-bit addressing. If NO, the conversion does not support 64-bit addressing.

$PAGES_TO_BYTES

Converts a page count to a byte count.

Format

$PAGES_TO_BYTES source_pagcnt, dest_bytcnt, leftshift, quad=YES

Parameters

source_pagcnt
Source page count.
dest_bytcnt
Destination of byte count.
leftshift
Location of application-provided value to shift (in place of multiply). This value is a function of the page size, as shown in Table D-1.
quad=YES
If YES, the conversion supports 64-bit addressing. If NO, the conversion does not support 64-bit addressing.

$PREVIOUS_PAGE

Computes the virtual address of the first byte in the previous page.

Format

$PREVIOUS_PAGE source_va, dest_va, clearbwp=NO, user_pagesize_addr, user_mask_addr, quad=YES

Parameters

source_va
Source virtual address.
dest_va
Destination of virtual address within previous page.
clearbwp=NO
If YES, masks the byte-within-page portion of the source virtual address. The clearbwp=NO option is a performance enhancement, avoiding unnecessary instructions if you know you are starting on a page boundary or you are intending to divide by page-size anyway.
user_pagesize_addr
Location of the page-size value (returned by a call to the $GETSYI system service specifying the SYI$_PAGESIZE item descriptor) in the application data area. If this argument is blank, the macro uses MMG$GL_PAGESIZE (bigpage) or MMG$C_VAX_PAGE_SIZE (vaxpage).
user_mask_addr
Location of the application-provided byte-within-page mask. If this argument is blank, the macro uses MMG$GL_BWP_MASK if user_pagesize_addr is also blank. Otherwise, it subtracts 1 from the contents of the user_pagesize_addr and uses that value.
quad=YES
If YES, the conversion supports 64-bit addressing. If NO, the conversion does not support 64-bit addressing.

Contents

Index

HP OpenVMS MACRO Compiler Porting and User's Guide

C.2 Alpha PALcode Built-Ins

C.3 Itanium Instruction Built-Ins for OpenVMS I64 Systems

Appendix DMacros for Porting from VAX to Alpha or I64

D.1 Calculating Page-Size Values

$BYTES_TO_PAGES

Format

Parameters

source_bytcnt

dest_pagcnt

rightshift

roundup=YES

quad=YES

$NEXT_PAGE

Format

Parameters

source_va

dest_va

clearbwp=NO

user_pagesize_addr

user_mask_addr

quad=YES

$PAGES_TO_BYTES

Format

Parameters

source_pagcnt

dest_bytcnt

leftshift

quad=YES

$PREVIOUS_PAGE

Format

Parameters

source_va

dest_va

clearbwp=NO

user_pagesize_addr

user_mask_addr

quad=YES

HP OpenVMS MACRO Compiler
Porting and User's Guide

Appendix D
Macros for Porting from VAX to Alpha or I64